use strict; use warnings; use Data::Dumper; my @modules; while(){ push @modules, { name => $1 } if /^module (\w+) \(.*\)/; $modules[ -1 ]->{ input } = [ split /,/, $1 ] if /^input (.*);/; $modules[ -1 ]->{ output } = [ split /,/, $1 ] if /^output (.*);/; $modules[ -1 ]->{ wire } = [ split /,/, $1 ] if /^wire (.*);/; next if /^endmodule/; if( /^(nand|nor|other)/ ) { push @{ $modules[ -1 ]->{ gates } }, {}; @{ $modules[ -1 ]->{ gates }[-1] }{ qw( type name output input_A input_B) } = split /[\s\(\),;]+/; } } print Dumper \@modules; __DATA__ module circuit_17 (N1,N2,N3,N6,N7,N22,N23); input N1,N2,N3,N6,N7; output N22,N23; wire N10,N11,N16,N19; nand nand2_1 (N10,N1,N3); nand nand2_2 (N11,N3,N6); nand nand2_3 (N16,N11,N2); nand nand2_4 (N19,N11,N7); nand nand2_5 (N22,N10,N16); nand nand2_6 (N23,N16,N19); endmodule