Why this code is not giving output for this file. Even I changed this line
Change in code "if ( $line =~ /([N01]{39})$/ )"
FILE:-
STIL 1.0 { Design 2005; }
Header {
Title " TetraMAX(R) K-2015.06-SP2-i150831_132851 STIL output";
Date "Sun Feb 4 16:53:01 2018";
Source " TetraMAX(R) K-2015.06-SP2-i150831_132851 STIL output";
History {
Ann {* Incoming_Date "Sun Feb 4 16:51:16 2018" *}
Ann {* Collapsed Transition Fault Summary Report *}
Ann {* ----------------------------------------------- *}
Ann {* fault class code #faults *}
Ann {* ------------------------------ ---- --------- *}
Ann {* Detected DT 64 *}
Ann {* Possibly detected PT 2 *}
Ann {* Undetectable UD 33 *}
Ann {* ATPG untestable AU 3059 *}
Ann {* Not detected ND 0 *}
Ann {* ----------------------------------------------- *}
Ann {* total faults 3158 *}
Ann {* test coverage 2.08% *}
Ann {* ----------------------------------------------- *}
Ann {* *}
Ann {* Pattern Summary Report *}
Ann {* ----------------------------------------------- *}
Ann {* #internal patterns 37 *}
Ann {* #full_sequential patterns 37 *}
Ann {* ----------------------------------------------- *}
Ann {* *}
Ann {* rule severity #fails description *}
Ann {* ---- -------- ------ ---------------------------------
+ *}
Ann {* N20 warning 1 underspecified UDP *}
Ann {* B8 warning 11 unconnected module input pin *}
Ann {* B9 warning 2 undriven module internal net *}
Ann {* B10 warning 147 unconnected module internal net *
+}
Ann {* C3 warning 145 no latch transparency when clocks
+ off *}
Ann {* C16 warning 145 nonscan cell port unable to captu
+re *}
Ann {* *}
Ann {* clock_name off usage *}
Ann {* ---------------- --- -------------------------- *}
Ann {* CK 0 *}
Ann {* *}
Ann {* There are no constraint ports *}
Ann {* There are no equivalent pins *}
Ann {* There are no net connections *}
Ann {* top_module_name = s9234 *}
Ann {* Unified STIL Flow *}
Ann {* serial_flag = 1 *}
}
}
Signals {
"GND" In; "VDD" In; "CK" In; "g102" In; "g107" In; "g22" In; "g23"
+In; "g301" In;
"g306" In; "g310" In; "g314" In; "g319" In; "g32" In; "g36" In; "g3
+7" In; "g38" In;
"g39" In; "g40" In; "g41" In; "g42" In; "g44" In; "g45" In; "g46" I
+n; "g47" In;
"g557" In; "g558" In; "g559" In; "g560" In; "g561" In; "g562" In; "
+g563" In; "g564" In;
"g567" In; "g639" In; "g702" In; "g705" In; "g89" In; "g94" In; "g9
+8" In; "g1290" Out;
"g1293" Out; "g2584" Out; "g3222" Out; "g3600" Out; "g4098" Out; "g
+4099" Out; "g4100" Out;
"g4101" Out; "g4102" Out; "g4103" Out; "g4104" Out; "g4105" Out; "g
+4106" Out; "g4107" Out;
"g4108" Out; "g4109" Out; "g4110" Out; "g4112" Out; "g4121" Out; "g
+4307" Out; "g4321" Out;
"g4422" Out; "g4809" Out; "g5137" Out; "g5468" Out; "g5469" Out; "g
+5692" Out; "g6282" Out;
"g6284" Out; "g6360" Out; "g6362" Out; "g6364" Out; "g6366" Out; "g
+6368" Out; "g6370" Out;
"g6372" Out; "g6374" Out; "g6728" Out;
}
SignalGroups {
"_pi" = '"GND" + "VDD" + "CK" + "g102" + "g107" + "g22" + "g23" + "
+g301" +
"g306" + "g310" + "g314" + "g319" + "g32" + "g36" + "g37" + "g38" +
+ "g39" +
"g40" + "g41" + "g42" + "g44" + "g45" + "g46" + "g47" + "g557" + "g
+558" +
"g559" + "g560" + "g561" + "g562" + "g563" + "g564" + "g567" + "g63
+9" +
"g702" + "g705" + "g89" + "g94" + "g98"' { WFCMap { 0X->0; 1X->1; Z
+X->Z;
NX->N; ZH->H; ZL->L; ZT->T; 1Z->1; 0Z->0; } } // #signals=39
"_in" = '"GND" + "VDD" + "CK" + "g102" + "g107" + "g22" + "g23" + "
+g301" +
"g306" + "g310" + "g314" + "g319" + "g32" + "g36" + "g37" + "g38" +
+ "g39" +
"g40" + "g41" + "g42" + "g44" + "g45" + "g46" + "g47" + "g557" + "g
+558" +
"g559" + "g560" + "g561" + "g562" + "g563" + "g564" + "g567" + "g63
+9" +
"g702" + "g705" + "g89" + "g94" + "g98"'; // #signals=39
"_po" = '"g1290" + "g1293" + "g2584" + "g3222" + "g3600" + "g4098"
++ "g4099" +
"g4100" + "g4101" + "g4102" + "g4103" + "g4104" + "g4105" + "g4106"
+ + "g4107" +
"g4108" + "g4109" + "g4110" + "g4112" + "g4121" + "g4307" + "g4321"
+ + "g4422" +
"g4809" + "g5137" + "g5468" + "g5469" + "g5692" + "g6282" + "g6284"
+ + "g6360" +
"g6362" + "g6364" + "g6366" + "g6368" + "g6370" + "g6372" + "g6374"
+ + "g6728"'
{ WFCMap { 0X->0; 1X->1; ZX->Z; NX->N; ZH->H; ZL->L; ZT->T; 1Z->1;
+0Z->0; } } // #signals=39
"_out" = '"g1290" + "g1293" + "g2584" + "g3222" + "g3600" + "g4098"
+ + "g4099" +
"g4100" + "g4101" + "g4102" + "g4103" + "g4104" + "g4105" + "g4106"
+ + "g4107" +
"g4108" + "g4109" + "g4110" + "g4112" + "g4121" + "g4307" + "g4321"
+ + "g4422" +
"g4809" + "g5137" + "g5468" + "g5469" + "g5692" + "g6282" + "g6284"
+ + "g6360" +
"g6362" + "g6364" + "g6366" + "g6368" + "g6370" + "g6372" + "g6374"
+ + "g6728"';
// #signals=39
"_default_In_Timing_" = '"GND" + "VDD" + "CK" + "g102" + "g107" + "
+g22" +
"g23" + "g301" + "g306" + "g310" + "g314" + "g319" + "g32" + "g36"
++ "g37" +
"g38" + "g39" + "g40" + "g41" + "g42" + "g44" + "g45" + "g46" + "g4
+7" +
"g557" + "g558" + "g559" + "g560" + "g561" + "g562" + "g563" + "g56
+4" +
"g567" + "g639" + "g702" + "g705" + "g89" + "g94" + "g98"'; // #sig
+nals=39
"_default_Out_Timing_" = '"g1290" + "g1293" + "g2584" + "g3222" + "
+g3600" +
"g4098" + "g4099" + "g4100" + "g4101" + "g4102" + "g4103" + "g4104"
+ + "g4105" +
"g4106" + "g4107" + "g4108" + "g4109" + "g4110" + "g4112" + "g4121"
+ + "g4307" +
"g4321" + "g4422" + "g4809" + "g5137" + "g5468" + "g5469" + "g5692"
+ + "g6282" +
"g6284" + "g6360" + "g6362" + "g6364" + "g6366" + "g6368" + "g6370"
+ + "g6372" +
"g6374" + "g6728"'; // #signals=39
"_default_Clk0_Timing_" = '"CK"'; // #signals=1
}
Timing {
WaveformTable "_default_WFT_" {
Period '100ns';
Waveforms {
"_default_In_Timing_" { 0 { '0ns' D; } }
"_default_In_Timing_" { 1 { '0ns' U; } }
"_default_In_Timing_" { Z { '0ns' Z; } }
"_default_In_Timing_" { N { '0ns' N; } }
"_default_Clk0_Timing_" { P { '0ns' D; '50ns' U; '80ns' D; }
+}
"_default_Out_Timing_" { X { '0ns' Z; } }
"_default_Out_Timing_" { H { '0ns' Z; '40ns' H; } }
"_default_Out_Timing_" { L { '0ns' Z; '40ns' L; } }
"_default_Out_Timing_" { T { '0ns' Z; '40ns' T; } }
}
}
}
ScanStructures {
// Uncomment and modify the following to suit your design
// ScanChain "chain_name" { ScanIn "chain_input_name"; ScanOut "cha
+in_output_name"; }
}
PatternBurst "_burst_" {
PatList { "_pattern_" {
}
}}
PatternExec {
PatternBurst "_burst_";
}
Procedures {
"multiclock_capture" {
W "_default_WFT_";
C { "VDD"=0; "g319"=0; "g314"=0; "g5692"=X; "g310"=0; "g4422"=X;
+ "g2584"=X; "g6368"=X; "g6366"=X; "g6364"=X;
"g6362"=X; "g6360"=X; "g6284"=X; "g4099"=X; "g6282"=X; "g4098
+"=X; "g6374"=X; "g6372"=X; "g6370"=X;
"g6728"=X; "g3600"=X; "g89"=0; "g5469"=X; "g5468"=X; "g4109"=
+X; "g4108"=X; "g4107"=X; "g4106"=X;
"g4105"=X; "g4104"=X; "g4103"=X; "g4102"=X; "g4101"=X; "g4100
+"=X; "g98"=0; "g94"=0; "g4809"=X; "g705"=0;
"g702"=0; "g4112"=X; "g4110"=X; "g107"=0; "g5137"=X; "g102"=0
+; "g4121"=X; "g639"=0; "g4307"=X; "g23"=0;
"g22"=0; "CK"=0; "g559"=0; "GND"=0; "g558"=0; "g557"=0; "g39"
+=0; "g38"=0; "g37"=0; "g36"=0; "g32"=0; "g567"=0;
"g564"=0; "g563"=0; "g562"=0; "g561"=0; "g1293"=X; "g560"=0;
+"g1290"=X; "g3222"=X; "g306"=0; "g47"=0;
"g46"=0; "g45"=0; "g44"=0; "g301"=0; "g42"=0; "g41"=0; "g40"=
+0; "g4321"=X; }
V { "_pi"=\j \r39 # ; "_po"=\j \r39 # ; }
}
"allclock_capture" {
W "_default_WFT_";
C { "VDD"=0; "g319"=0; "g314"=0; "g5692"=X; "g310"=0; "g4422"=X;
+ "g2584"=X; "g6368"=X; "g6366"=X; "g6364"=X;
"g6362"=X; "g6360"=X; "g6284"=X; "g4099"=X; "g6282"=X; "g4098
+"=X; "g6374"=X; "g6372"=X; "g6370"=X;
"g6728"=X; "g3600"=X; "g89"=0; "g5469"=X; "g5468"=X; "g4109"=
+X; "g4108"=X; "g4107"=X; "g4106"=X;
"g4105"=X; "g4104"=X; "g4103"=X; "g4102"=X; "g4101"=X; "g4100
+"=X; "g98"=0; "g94"=0; "g4809"=X; "g705"=0;
"g702"=0; "g4112"=X; "g4110"=X; "g107"=0; "g5137"=X; "g102"=0
+; "g4121"=X; "g639"=0; "g4307"=X; "g23"=0;
"g22"=0; "CK"=0; "g559"=0; "GND"=0; "g558"=0; "g557"=0; "g39"
+=0; "g38"=0; "g37"=0; "g36"=0; "g32"=0; "g567"=0;
"g564"=0; "g563"=0; "g562"=0; "g561"=0; "g1293"=X; "g560"=0;
+"g1290"=X; "g3222"=X; "g306"=0; "g47"=0;
"g46"=0; "g45"=0; "g44"=0; "g301"=0; "g42"=0; "g41"=0; "g40"=
+0; "g4321"=X; }
V { "_pi"=\j \r39 # ; "_po"=\j \r39 # ; }
}
"allclock_launch" {
W "_default_WFT_";
C { "VDD"=0; "g319"=0; "g314"=0; "g5692"=X; "g310"=0; "g4422"=X;
+ "g2584"=X; "g6368"=X; "g6366"=X; "g6364"=X;
"g6362"=X; "g6360"=X; "g6284"=X; "g4099"=X; "g6282"=X; "g4098
+"=X; "g6374"=X; "g6372"=X; "g6370"=X;
"g6728"=X; "g3600"=X; "g89"=0; "g5469"=X; "g5468"=X; "g4109"=
+X; "g4108"=X; "g4107"=X; "g4106"=X;
"g4105"=X; "g4104"=X; "g4103"=X; "g4102"=X; "g4101"=X; "g4100
+"=X; "g98"=0; "g94"=0; "g4809"=X; "g705"=0;
"g702"=0; "g4112"=X; "g4110"=X; "g107"=0; "g5137"=X; "g102"=0
+; "g4121"=X; "g639"=0; "g4307"=X; "g23"=0;
"g22"=0; "CK"=0; "g559"=0; "GND"=0; "g558"=0; "g557"=0; "g39"
+=0; "g38"=0; "g37"=0; "g36"=0; "g32"=0; "g567"=0;
"g564"=0; "g563"=0; "g562"=0; "g561"=0; "g1293"=X; "g560"=0;
+"g1290"=X; "g3222"=X; "g306"=0; "g47"=0;
"g46"=0; "g45"=0; "g44"=0; "g301"=0; "g42"=0; "g41"=0; "g40"=
+0; "g4321"=X; }
V { "_pi"=\j \r39 # ; "_po"=\j \r39 # ; }
}
"allclock_launch_capture" {
W "_default_WFT_";
C { "VDD"=0; "g319"=0; "g314"=0; "g5692"=X; "g310"=0; "g4422"=X;
+ "g2584"=X; "g6368"=X; "g6366"=X; "g6364"=X;
"g6362"=X; "g6360"=X; "g6284"=X; "g4099"=X; "g6282"=X; "g4098
+"=X; "g6374"=X; "g6372"=X; "g6370"=X;
"g6728"=X; "g3600"=X; "g89"=0; "g5469"=X; "g5468"=X; "g4109"=
+X; "g4108"=X; "g4107"=X; "g4106"=X;
"g4105"=X; "g4104"=X; "g4103"=X; "g4102"=X; "g4101"=X; "g4100
+"=X; "g98"=0; "g94"=0; "g4809"=X; "g705"=0;
"g702"=0; "g4112"=X; "g4110"=X; "g107"=0; "g5137"=X; "g102"=0
+; "g4121"=X; "g639"=0; "g4307"=X; "g23"=0;
"g22"=0; "CK"=0; "g559"=0; "GND"=0; "g558"=0; "g557"=0; "g39"
+=0; "g38"=0; "g37"=0; "g36"=0; "g32"=0; "g567"=0;
"g564"=0; "g563"=0; "g562"=0; "g561"=0; "g1293"=X; "g560"=0;
+"g1290"=X; "g3222"=X; "g306"=0; "g47"=0;
"g46"=0; "g45"=0; "g44"=0; "g301"=0; "g42"=0; "g41"=0; "g40"=
+0; "g4321"=X; }
V { "_pi"=\j \r39 # ; "_po"=\j \r39 # ; }
}
// Uncomment and modify the following to suit your design
// load_unload {
// V { "CK" = 0; } // force clocks off and scan enable pins acti
+ve
// Shift { V { _si=#; _so=#; "CK" = P; }} // pulse shift clocks
// }
}
MacroDefs {
"test_setup" {
W "_default_WFT_";
V { "CK"=0; }
}
}
Pattern "_pattern_" {
W "_default_WFT_";
"precondition all Signals": C { "_pi"=\r39 0 ; "_po"=\r39 X ; }
Macro "test_setup";
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNN0NNNNNNNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNN1NNNNNNNNNNNNNNNNNNNNNNNN; "_po"=XXXXXXXXHXX
+XXXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNN1NNNNNNNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNN0NNNNNNNNNNNNNNNNNNNNNNNN; "_po"=XXXXXXXXLXX
+XXXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNN0NNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNN1NNNNNNNNNNNNNNNNNN; "_po"=XXXXXXXXXXX
+XXXHXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN0NN; }
Call "allclock_launch_capture" {
"_pi"=NN00NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN1NN; "_po"=XXHXXXXXXXX
+XXXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN0NNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN1NNN; "_po"=XXXHXXXXXXX
+XXXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNN0NNNNNNNNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNN1NNNNNNNNNNNNNNNNNNNNNNNNN; "_po"=XXXXXXXHXXX
+XXXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNN0NNNNNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNNN1NNNNNNNNNNNNNNNNNNNNNN; "_po"=XXXXXXXXXXH
+XXXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNNN0NNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNNN1NNNNNNNNNNNNNNNN; "_po"=XXXXXXXXXXX
+XXXXXHXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNN0NNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNN1NNNNNNNNNNNNNNNNNNN; "_po"=XXXXXXXXXXX
+XXHXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN1NN; }
Call "allclock_launch_capture" {
"_pi"=NN00NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN0NN; "_po"=XXLXXXXXXXX
+XXXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNNNN1NNNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNNNNN0NNNNNNNNNNNNNNNNNNNN; "_po"=XXXXXXXXXXX
+XXXXXXLXXXXXXXXXLXHHHHHHHHHL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNN1NNNNNNNNNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNN0NNNNNNNNNNNNNNNNNNNNNNNNNN; "_po"=XXXXXXLXXXX
+XXXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNN1NNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNN0NNNNNNNNNNNNNNNNNNN; "_po"=XXXXXXXXXXX
+XXLXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNNNN0NNNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNNNNN1NNNNNNNNNNNNNNNNNNNN; "_po"=XXXXXXXXXXX
+XXXXXXHXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNN0NNNNNNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNN1NNNNNNNNNNNNNNNNNNNNNNN; "_po"=XXXXXXXXXHX
+XXXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN00NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN1NN; }
Call "allclock_launch_capture" {
"_pi"=NN01NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN; "_po"=XXLXXXXXXXX
+XXXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN00NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN01NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN1NN; "_po"=XXLXXXXXXXX
+XXXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN01NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN00NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN1NN; "_po"=XXHXXXXXXXX
+XXXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NN0NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NN1NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN; "_po"=XXXXXXXXXXX
+HXXXXXXXXXXXXXXXLHHHHHHHHHHL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NN1NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NN0NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN; "_po"=XXXXXXXXXXX
+LXXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNN0NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNN1NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN; "_po"=XXXXXHXXXXX
+XXXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNN1NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNN0NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN; "_po"=XXXXXLXXXXX
+XXXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNN0NNNNNNNNNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNN1NNNNNNNNNNNNNNNNNNNNNNNNNN; "_po"=XXXXXXHXXXX
+XXXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNN1NNNNNNNNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNN0NNNNNNNNNNNNNNNNNNNNNNNNN; "_po"=XXXXXXXLXXX
+XXXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNN1NNNNNNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNN0NNNNNNNNNNNNNNNNNNNNNNN; "_po"=XXXXXXXXXLX
+XXXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNN1NNNNNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNNN0NNNNNNNNNNNNNNNNNNNNNN; "_po"=XXXXXXXXXXL
+XXXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNNN0NNNNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNNNN1NNNNNNNNNNNNNNNNNNNNN; "_po"=XXXXXXXXXXX
+XHXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNNN1NNNNNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNNNN0NNNNNNNNNNNNNNNNNNNNN; "_po"=XXXXXXXXXXX
+XLXXXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNN1NNNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNN0NNNNNNNNNNNNNNNNNN; "_po"=XXXXXXXXXXX
+XXXLXXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNN0NNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNN1NNNNNNNNNNNNNNNNN; "_po"=XXXXXXXXXXX
+XXXXHXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNN1NNNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNN0NNNNNNNNNNNNNNNNN; "_po"=XXXXXXXXXXX
+XXXXLXXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNNN1NNNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNNN0NNNNNNNNNNNNNNNN; "_po"=XXXXXXXXXXX
+XXXXXLXXXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNNNN0NNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNNNN1NNNNNNNNNNNNNNN; "_po"=XXXXXXXXXXX
+XXXXXXXHXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNNNN1NNNNNNNNNNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNNNN0NNNNNNNNNNNNNNN; "_po"=XXXXXXXXXXX
+XXXXXXXLXXXXXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNNNNNNNNNNNN0NNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNNNNNNNNNNNN1NNNNNNN; "_po"=XXXXXXXXXXX
+XXXXXXXXXXXHXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNNNNNNNNNNNN1NNNNNNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNNNNNNNNNNNN0NNNNNNN; "_po"=XXXXXXXXXXX
+XXXXXXXXXXXLXXXXLXXXXXXXXXXL; }
Ann {* full_sequential *}
Call "multiclock_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN1NNN; }
Call "allclock_launch_capture" {
"_pi"=NN0NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN0NNN; "_po"=XXXLXXXXXXX
+XXXXXXXXXXXXXXXXLXXXXXXXXXXL; }
}
// Patterns reference 75 V statements, generating 75 test cycles
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