Re^3: Someone please verify this. (Verilog::VCD)


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Re^3: Someone please verify this. (Verilog::VCD)

by toolic (Bishop)

on Jan 22, 2012 at 13:55 UTC ( [id://949252]=note: print w/replies, xml )

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in reply to Re^2: Someone please verify this. (Verilog::VCD)
in thread Someone please verify this.

You are right... Verilog::VCD can only be used to parse VCD files. It can not create a VCD file. I am not aware of any CPAN module which can create a VCD file. This looks like an opportunity for you to contribute.

Why do you need Perl code to create a VCD file? All Verilog simulators can create VCD files.

Comment on Re^3: Someone please verify this. (Verilog::VCD)

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Re^4: Someone please verify this. (Verilog::VCD) by sarodeoa (Initiate) on Jan 23, 2012 at 00:07 UTC
Thanks for your reply. I do have a requirement to create a VCD from a dump of values (a set of samples captured from an on chip memory) -- so that it is better from readability/debug point of view. Hopefully, when i am done with my script, i can contribute some CreateVCD module -- lets see :) Thanks.	[reply]
Re^5: Someone please verify this. (Verilog::VCD) by vijayvithal (Novice) on May 19, 2017 at 17:19 UTC
sarodeoa toolic, FYI, I have uploaded a VCD writer to prePAN today. http://prepan.org/module/nYdTCdrkEHF	[reply]

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