There are modules on CPAN that can do it for you. Maybe Verilog::Parser or Verilog::SigParser?

If you need to parse some auto-generated file or a restricted subset of the language, you stand a better chance. Is your example data auto-generated? Who but a machine would omit the carriage return following the ";" before the always block?

I don't know what you want to DO with the always block (and the rest of that Verilog code). What are you building in Perl and what data do you want to collect from the code to make it happen?

For your example code block, it is straightforward to pull out the clock, the reset (and it's polarity) and the expression this DFF uses. The next always block might be a latch, or a flop with synchronous reset, or no reset, or have multiple signals, or use SystemVerilog always_ff, or be an entire state-machine, or call a task, etc. In short, you need a language parser.

My advice is to use, or build on, what exists if possible. If not, then restrict what you are doing and start small.

Use the diamond operator to read the file/data. When a line starts with "//always" it triggers the begin of the block. You can use a Regular Expression to test this. Keep reading until you encounter an "//end" it's the end of the block. This should be straightforward.

Update

Something you can play with. You'll get the idea.

use strict;
use warnings;

while (my $line=<DATA>){
    if ($line =~ /\/\/always/){
        print "Start of block\n";
    }
    if ($line =~ /end\/\//) {
        print "End of block\n";    
    }
}

__DATA__
input [31:0]           ucast_mem_wdata;
   input [31:0]           ucast_mem_wren;
   input               ucast_mem_wr;
   input               ucast_mem_rd;
   output [31:0]           ucast_mem_rdata;

   wire [BMU_MEM_ADDR_BITS-1:0]   mem_addr; 
//always @ (posedge sys_clk or negedge sys_reset_n)
     begin
    if (!sys_reset_n)
      ucast_int_mem_rd_r <= 0;
    else
      ucast_int_mem_rd_r <= ucast_int_mem_rd & !ucast_access;
     end// this is the always block which i have to read into another 
+file
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Here are some of the common pitfalls you are facing (and there are many, many more):

• What if there are ports or always blocks inside comments, both single-line (//) and multi-line (/**/)?
• What if someone used `include or `define compiler directives to declare ports?
• What if there are functions declared within a module, which have their own ports?
• How do you reliably determine the end of an always block? There is no "always_end" construct.
• How do you deal with IEEE Std 2001 syntax for ports?

Here are some techniques I have used to overcome some of these issues. You could pre-process the Verilog file to remove all comments using the regex in perlfaq6:

How do I use a regular expression to strip C style comments from a file?

This will work in most (but not all) cases.

If you have access to the Cadence ncverilog simulation tools, you could first compile the Verilog files, then de-compile the files using ncdc. This tool allows for some control over the resulting de-compiled files so that parsing may be simpler. I am not sure if other simulation tools have the same capability.

If you can edit the Verilog source files, you could embed pragmas in comments such as // always_end -- but that will only help you for future development.

That being said, here is some EXTREMELY BRITTLE code which works for the Verilog code you provided:

use strict;
use warnings;

my @ins;
my @outs;
my @blocks;
my $flag = 0;
while (<DATA>) {
    if (/\binput\b/)  { push @ins , $_ }
    if (/\boutput\b/) { push @outs, $_ }
    if (/\balways\b/) {
        s/^.*\b(always)\b/$1/;
        push @blocks, $_;
        $flag = 1;
        next;
    }
    if ($flag) {
        push @blocks, $_;
        $flag = 0 if (/^\s*$/); # blank line ends always block
    }
}

create_file('inputs.v' , @ins);
create_file('outputs.v', @outs);
create_file('always.v' , @blocks);

sub create_file {
    my $file = shift;
    open my $fileHandle, '>', $file or die "Unable to create $file: $!
+\n";
    print $fileHandle $_ for (@_);
    close $fileHandle or die "Unable to close file $file: $!\n";
}

__DATA__
   input [31:0]           ucast_mem_wdata;
   input [31:0]           ucast_mem_wren;
   input               ucast_mem_wr;
   input               ucast_mem_rd;
   output [31:0]           ucast_mem_rdata;

   wire [BMU_MEM_ADDR_BITS-1:0]   mem_addr; always @ (posedge sys_clk 
+or negedge sys_reset_n)
     begin
    if (!sys_reset_n)
      ucast_int_mem_rd_r <= 0;
    else
      ucast_int_mem_rd_r <= ucast_int_mem_rd & !ucast_access;
     end


endmodule
[download]

Here is the output:

I have difficulty understanding this. Could you use some formatting to make the text more readable? See Perl Monks Approved HTML tags for the possibilities.

Now i have formatted it.Please dont understanding me wrong,here for me all features are looking bit difficult in using them.Now you can have a look at that.Thank you

   input [31:0]           ucast_mem_wdata;
   input [31:0]           ucast_mem_wren;
   input               ucast_mem_wr;
   input               ucast_mem_rd;
   output [31:0]           ucast_mem_rdata;

   wire [BMU_MEM_ADDR_BITS-1:0]   mem_addr; always @ (posedge sys_clk 
+or negedge sys_reset_n)
     begin
    if (!sys_reset_n)
      ucast_int_mem_rd_r <= 0;
    else
      ucast_int_mem_rd_r <= ucast_int_mem_rd &amp; !ucast_access;
     end


endmodule
[download]

I am having the pblm at reading always block as it is so many internal blocks

could u anybody tell me how to read entire always block and write it to the socalled named file THis is the code I tried for input and out put reading

but i couldnt get any idea regarding the reading of whole always blcok for the above

your attempt from ravi030's scratchpad

#!usr/bin/perl

use strict;
use warnings;

open(
    my $ip_fileh, '<',

    "D:\\PacketProcessor\\rtl\\common\\gen_sync_fifo.v"
  )
  || die

  (
    "unable to open the file 

D:\\PacketProcessor\\rtl\\common\\gen_sync_fifo.v\n"
  );    #open the file

while (<$ip_fileh>) {    #read the file line by line

    my $str = $_;        #assign to a variable

    chomp $str;          #remove the new line

    if ( $str =~ m/(Input|output) ((\w+(,\s*\w+)*)|([^\n]*))/i ) {

        my $type = $1;    #get whether input or output

        my @inp_vals = split /\,\s*/, $2;    #split by comma followed 
+by space if more than one values

          local $" = "\n";    #to print the array values line by line

        print "$type\n@inp_vals \n";    #print the output

    }

}

__END__
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