Hi all..

My original file FA.vhd is as follows...

component MAJ3
    port( A : in    std_logic := 'U';
enable : in std_logic;          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
end component;

signal \GND\, \VCC\, N_5, a_c, b_c, c_c, sum_c, GND_0, VCC_0
         : std_logic;

begin 
enable_pad : INBUF port map (PAD => enable, Y => enable_c);
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i have one more file enabled_nets.txt that has follwoing lines..

a_e
b_e
c_e
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i want to modify the signal declaration statement in FA.vhd as

signal \GND\, \VCC\, N_5, a_c, b_c, c_c, sum_c, GND_0, 

VCC_0, a_e, b_e, c_e, enable_c: std_logic;
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i.e. i want to include the words in enabled_nets.txt to signal declaration part of FA.vhd as mentioned above, along with this i want to add one more signal enable_c also, and all these word need to be comma separated... Here is the perl script i have written for this... Correct the mistake in it monks.... Thank you all for your valuable time....

open (IN1, "<FA.vhd") or die;
open (OUT, ">common_modify.vhd") or die;

while (<IN1>) {
print OUT;
    if (/signal/){
    open (IN2, "<enabled_nets.txt") or die;
    my @enabled_nets = <IN2>;
    chomp @enabled_nets;
        while (<IN2>) {
            print OUT ; 
            print OUT ',enable_c,';
        }
    close (IN2);
    }
}
close (IN1);
close (OUT);
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