A few tips:

1. Your regex is not the best. .* is "dangerous" and fraught with unintended consequences. You can go far with just \w and \s.
2. Forget this $1,$2 stuff. Assign directly as shown below
3. The if() is true if the regex matches, else it is false. as shown below
4. I have many question, but this will help you get started...

#!/usr/bin/perl
use strict;
use warnings;
use Data::Dumper;

my @gate_data;

while (my $line = <DATA>)
{
    if (my($gate_type,$gate_name,$ouput_gate,$input_A, $input_B)
          = $line =~ /^(\w+)\s+(\w+)\s+\((\w+),(\w+),(\w+)\)/)
    {          
      print "$gate_type, $gate_name,$ ouput_gate, $input_A, $input_B\n
+";
      push @gate_data,[$gate_type, $gate_name,$ ouput_gate, $input_A, 
+$input_B];
    }
}


print "@$_\n" for @gate_data;

=prints
nand, nand2_1,N10, N1, N3
nand, nand2_2,N11, N3, N6
nand, nand2_3,N16, N11, N2
nand, nand2_4,N19, N11, N7
nand, nand2_5,N22, N10, N16
nand, nand2_6,N23, N16, N19
nand nand2_1 N10 N1 N3
nand nand2_2 N11 N3 N6
nand nand2_3 N16 N11 N2
nand nand2_4 N19 N11 N7
nand nand2_5 N22 N10 N16
nand nand2_6 N23 N16 N19
=cut

__DATA__
module circuit_17 (N1,N2,N3,N6,N7,N22,N23);
input N1,N2,N3,N6,N7;
output N22,N23;
wire N10,N11,N16,N19;
nand nand2_1 (N10,N1,N3);
nand nand2_2 (N11,N3,N6);
nand nand2_3 (N16,N11,N2);
nand nand2_4 (N19,N11,N7);
nand nand2_5 (N22,N10,N16);
nand nand2_6 (N23,N16,N19);
endmodule
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Update: It appears that this output is coming from sort of wiring program. What you show here is the human readable output. There will another form of output designed as input for whatever machine is going to further fiddle with this data. I suggest you forget about parsing this data format and get whatever that other data output is. It will already be structured into records designed to handle all of the various gate types and other parts like flip-flops, registers, etc. Reverse engineering that data structure seems pointless to me.