component MAJ3
    port( A : in    std_logic := 'U';
enable : in std_logic;          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
end component;

signal \GND\, \VCC\, N_5, a_c, b_c, c_c, sum_c, GND_0, VCC_0
         : std_logic;

begin 
enable_pad : INBUF port map (PAD => enable, Y => enable_c);