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while (<DATA>) {
    s/\b module \s+ OLD \b/module NEW/xms;
    print $_;
}

__DATA__
 //Verilog HDL for "tt", "hh" "functional"
...
    input B;

endmodule

 //Verilog HDL for "tt", "hh" "functional"
// if i write the word module here the script goofs up
...
    input B;

endmodule