while (<DATA>) {
    s/\b module \s+ OLD \b/module NEW/xms;
    print $_;
}

##</code><code>##

__DATA__
 //Verilog HDL for "tt", "hh" "functional"
// if i write the word module here the script goofs up
`timescale 1ps/10fs


module OLD(Y, A, B ); // This is a great module!
    output Y;
    input A;
    input B;

endmodule

##</code><code>##

 //Verilog HDL for "tt", "hh" "functional"
// if i write the word module here the script goofs up
`timescale 1ps/10fs


module NEW(Y, A, B ); // This is a great module!
    output Y;
    input A;
    input B;

endmodule