component MAJ3
port( A : in std_logic := 'U';
enable : in std_logic; B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
signal \GND\, \VCC\, N_5, a_c, b_c, c_c, sum_c, GND_0, VCC_0
: std_logic;
begin
enable_pad : INBUF port map (PAD => enable, Y => enable_c);
####
a_e
b_e
c_e
##
##
signal \GND\, \VCC\, N_5, a_c, b_c, c_c, sum_c, GND_0,
VCC_0, a_e, b_e, c_e, enable_c: std_logic;
##
##
open (IN1, "common_modify.vhd") or die;
while () {
print OUT;
if (/signal/){
open (IN2, ";
chomp @enabled_nets;
while () {
print OUT ;
print OUT ',enable_c,';
}
close (IN2);
}
}
close (IN1);
close (OUT);